Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
authorMarvin Hsu <[email protected]>
Tue, 11 Apr 2017 03:00:48 +0000 (11:00 +0800)
committerVarun Wadekar <[email protected]>
Wed, 16 Jan 2019 18:11:18 +0000 (10:11 -0800)
commitce3c97c95b20f02f60cae5dc17b08b3c74615a74
tree7eaca38e1c7c093e8f4ee32f3fc10d71f5455c78
parent1d49112b2ac07b2130a0fe3850b36ac7c201ae13
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)

This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.

Change-Id: Ic80843902af70e76415530266cb158f668976c42
Signed-off-by: Marvin Hsu <[email protected]>
Signed-off-by: Varun Wadekar <[email protected]>
plat/nvidia/tegra/include/drivers/security_engine.h [new file with mode: 0644]
plat/nvidia/tegra/include/t210/tegra_def.h
plat/nvidia/tegra/soc/t210/drivers/se/se_private.h [new file with mode: 0644]
plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c [new file with mode: 0644]
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
plat/nvidia/tegra/soc/t210/plat_setup.c
plat/nvidia/tegra/soc/t210/platform_t210.mk